mirror of
https://git.vladimir.cc/vladimir/ewsdr.git
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589 lines
23 KiB
ObjectPascal
589 lines
23 KiB
ObjectPascal
{
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Copyright (C)
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2026 - Uladzimir Karpenka, EW8BAK
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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}
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unit HPSDRProtocol;
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{
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openHPSDR Ethernet Protocol V4.3 constants and packet structures.
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Big-Endian (Network Byte Order) unless otherwise noted.
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}
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{$IFDEF FPC}
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{$MODE Delphi}
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{$ENDIF}
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interface
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// ---------------------------------------------------------------------------
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// UDP Ports (defaults)
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// ---------------------------------------------------------------------------
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const
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PORT_COMMAND = 1024; // Discovery, Erase, Program, Set IP
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PORT_DDC_SPECIFIC = 1025; // DDC Specific packet (PC -> HW)
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PORT_DUC_SPECIFIC = 1026; // DUC/TXA Specific packet (PC -> HW)
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PORT_HP_FROM_PC = 1027; // High Priority from PC
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PORT_HP_TO_PC = 1025; // High Priority Status from HW
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PORT_DDC_AUDIO = 1028; // DDC Audio (PC -> HW)
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PORT_DUC_IQ = 1029; // DUC I&Q data (PC -> HW)
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PORT_MIC_DATA = 1026; // Microphone data (HW -> PC)
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PORT_WIDEBAND_ADC0 = 1027; // Wideband data (HW -> PC)
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PORT_DDC0_IQ = 1035; // DDC0 I&Q (HW -> PC), DDC1=1036 etc.
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// ---------------------------------------------------------------------------
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// Command bytes (Byte 4 of packet)
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// ---------------------------------------------------------------------------
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CMD_GENERAL = $00;
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CMD_DISCOVERY = $02;
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CMD_SET_IP = $03;
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CMD_ERASE = $04;
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CMD_PROGRAM = $05;
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// ---------------------------------------------------------------------------
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// Discovery Reply Byte 4
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// ---------------------------------------------------------------------------
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REPLY_DISCOVERY_FREE = $02; // Hardware available
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REPLY_DISCOVERY_INUSE = $03; // Hardware in use by another host
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REPLY_XML_DESC = $FE; // XML hardware description follows
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REPLY_FULL_DESC = $FF; // Full hardware description follows
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// ---------------------------------------------------------------------------
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// Board types (Discovery Reply Byte 11)
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// ---------------------------------------------------------------------------
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BOARD_ATLAS = 0;
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BOARD_HERMES = 1; // ANAN-10, 100
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BOARD_HERMES_10E = 2; // ANAN-10E, 100B
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BOARD_ANGELA = 3; // ANAN-100D
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BOARD_ORION = 4; // ANAN-200D
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BOARD_ORION_MK2 = 5; // ANAN-7/8000DLE
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BOARD_HERMES_LITE = 6;
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BOARD_SATURN = 10; // ANAN-G2
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// ---------------------------------------------------------------------------
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// Packet sizes
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// ---------------------------------------------------------------------------
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DISCOVERY_PACKET_SIZE = 60;
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GENERAL_PACKET_SIZE = 60;
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DDC_SPECIFIC_SIZE = 1444;
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DUC_SPECIFIC_SIZE = 60;
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HP_DATA_PC_SIZE = 1444;
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HP_STATUS_HW_SIZE = 60;
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DDC_AUDIO_SIZE = 260; // 4 hdr + 64*2*2
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DUC_IQ_SIZE = 1444; // 4 hdr + 240*6
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MIC_DATA_SIZE = 132; // 4 hdr + 64*2
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DDC_IQ_SIZE = 1444; // 4 hdr + 12 info + 238*6
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// ---------------------------------------------------------------------------
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// DDC sample rates (ksps)
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// ---------------------------------------------------------------------------
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DDC_RATE_48 = 48;
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DDC_RATE_96 = 96;
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DDC_RATE_192 = 192;
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DDC_RATE_384 = 384;
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DDC_RATE_768 = 768;
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DDC_RATE_1536 = 1536;
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// ---------------------------------------------------------------------------
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// DSP clock (Hz)
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// ---------------------------------------------------------------------------
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DSP_CLOCK_HZ: Double = 122880000.0;
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// ---------------------------------------------------------------------------
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// Maximum DDCs / ADCs
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// ---------------------------------------------------------------------------
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MAX_DDCS = 80;
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MAX_ADCS = 8;
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MAX_DUCS = 4;
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// ---------------------------------------------------------------------------
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// High Priority Byte 4 bits (PC -> HW)
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// ---------------------------------------------------------------------------
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HP_RUN = $01;
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HP_PTT0 = $02;
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HP_PTT1 = $04;
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HP_PTT2 = $08;
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HP_PTT3 = $10;
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// ---------------------------------------------------------------------------
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// High Priority Status Byte 4 bits (HW -> PC)
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// ---------------------------------------------------------------------------
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HPS_PTT = $01;
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HPS_DOT = $02;
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HPS_DASH = $04;
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HPS_PLL_LOCKED = $10;
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HPS_FIFO_EMPTY = $20;
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HPS_FIFO_FULL = $40;
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// ---------------------------------------------------------------------------
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// DUC Specific Byte 5 bits (CW options)
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// ---------------------------------------------------------------------------
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CW_EER = $01;
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CW_MODE = $02;
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CW_REVERSE_KEYS = $04;
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CW_IAMBIC = $08;
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CW_SIDETONE = $10;
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CW_MODE_B = $20;
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CW_STRICT_SPACING = $40;
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CW_BREAK_IN = $80;
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// ---------------------------------------------------------------------------
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// Packet record types
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// ---------------------------------------------------------------------------
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type
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// Raw byte array for a generic 60-byte command packet
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TRawPacket60 = array[0..59] of Byte;
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TRawPacket1444 = array[0..1443] of Byte;
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PRawPacket1444 = ^TRawPacket1444;
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PRawPacket60 = ^TRawPacket60;
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// -------------------------------------------------------------------------
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// Discovery packet (PC -> HW)
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// -------------------------------------------------------------------------
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TDiscoveryPacket = packed record
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SeqHi, SeqMidHi, SeqMidLo, SeqLo: Byte; // Bytes 0-3: always 0
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Command: Byte; // Byte 4: CMD_DISCOVERY=$02
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Zeros: array[5..59] of Byte; // Bytes 5-59: zero
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end;
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// -------------------------------------------------------------------------
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// Discovery Reply (HW -> PC)
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// -------------------------------------------------------------------------
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TDiscoveryReply = packed record
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SeqHi, SeqMidHi, SeqMidLo, SeqLo: Byte; // 0-3
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Status: Byte; // 4: $02 free/$03 in use
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MAC: array[0..5] of Byte; // 5-10
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BoardType: Byte; // 11
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ProtocolVersion: Byte; // 12
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FirmwareVersion: Byte; // 13
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Mercury0: Byte; // 14
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Mercury1: Byte; // 15
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Mercury2: Byte; // 16
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Mercury3: Byte; // 17
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PennyVersion: Byte; // 18
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MetisVersion: Byte; // 19
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NumDDCs: Byte; // 20
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FreqOrPhase: Byte; // 21: 0=freq, 1=phase
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EndianModes: Byte; // 22
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BetaVersion: Byte; // 23
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Reserved: array[24..59] of Byte;
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end;
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// -------------------------------------------------------------------------
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// General Packet (PC -> HW, port 1024)
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// -------------------------------------------------------------------------
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TGeneralPacket = packed record
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Seq: array[0..3] of Byte; // 0-3
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Command: Byte; // 4: CMD_GENERAL=$00
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DDCSpecPort: array[0..1] of Byte; // 5-6: default 1025
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DUCSpecPort: array[0..1] of Byte; // 7-8: default 1026
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HPFromPCPort: array[0..1] of Byte; // 9-10: default 1027
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HPToPCPort: array[0..1] of Byte; // 11-12: default 1025
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DDCAudioPort: array[0..1] of Byte; // 13-14: default 1028
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DUCIQPort: array[0..1] of Byte; // 15-16: default 1029
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DDC0Port: array[0..1] of Byte; // 17-18: default 1035
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MicPort: array[0..1] of Byte; // 19-20: default 1026
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WBPort: array[0..1] of Byte; // 21-22: default 1027
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WBEnable: Byte; // 23
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WBSamplesPerPkt: array[0..1] of Byte; // 24-25: default 512
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WBSampleSize: Byte; // 26: default 16
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WBUpdateRate: Byte; // 27: 0-255ms
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WBPacketsPerFrame: Byte; // 28: default 32
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MemMapFromPCPort: array[0..1] of Byte; // 29-30
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MemMapToPCPort: array[0..1] of Byte; // 31-32
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EnvPWMMin: array[0..1] of Byte; // 33-34
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EnvPWMMax: array[0..1] of Byte; // 35-36
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Flags37: Byte; // 37: timestamp/VITA/VNA/phase
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Flags38: Byte; // 38: HW timer enable
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DataFormat: Byte; // 39: endian/format
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Reserved40: array[40..55] of Byte;
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AtlasBusConfig: Byte; // 56: Atlas config [2:0]
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Ref10MHz: Byte; // 57: 10MHz source [1:0]
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PAConfig: Byte; // 58: PA/Apollo/Mercury/clock
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AlexEnable: Byte; // 59: Alex[0..7] enable
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end;
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// -------------------------------------------------------------------------
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// DDC Specific Packet (PC -> HW)
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// -------------------------------------------------------------------------
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TDDCSpecificPacket = packed record
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Seq: array[0..3] of Byte; // 0-3
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NumADCs: Byte; // 4: number of ADCs
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DitherADC: Byte; // 5: dither enable bits
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RandomADC: Byte; // 6: random enable bits
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DDCEnable: array[0..9] of Byte; // 7-16: enable bits DDC0..79
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// DDC config: 6 bytes each for DDC0..79
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// Byte 17+n*6: ADC selection
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// Byte 18+n*6: SampleRate [15:8]
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// Byte 19+n*6: SampleRate [7:0]
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// Byte 20+n*6: CIC1 (future)
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// Byte 21+n*6: CIC2 (future)
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// Byte 22+n*6: SampleSize (default 24)
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DDCConfig: array[0..479] of Byte; // 17-496
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Filler: array[497..1362] of Byte;
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SyncDDC: array[0..79] of Byte; // 1363-1442
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Unused: Byte; // 1443
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end;
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// Per-DDC config helper (maps into DDCConfig array above)
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TDDCConfig = packed record
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ADCSource: Byte; // which ADC (0..NumADCs-1) or NumADCs for DAC
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SampleRateHi, SampleRateLo: Byte;
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CIC1, CIC2: Byte;
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SampleSize: Byte; // default 24
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end;
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// -------------------------------------------------------------------------
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// DUC (Transmitter) Specific Packet (PC -> HW)
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// -------------------------------------------------------------------------
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TDUCSpecificPacket = packed record
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Seq: array[0..3] of Byte;
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NumDACs: Byte; // 4
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CWOptions: Byte; // 5: CW_* flags
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SidetoneLevel: Byte; // 6: 0..127
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SidetoneFreqHi: Byte; // 7
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SidetoneFreqLo: Byte; // 8
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KeyerSpeed: Byte; // 9: 0..60 WPM
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KeyerWeight: Byte; // 10: 33..66
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HangDelayHi: Byte; // 11
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HangDelayLo: Byte; // 12
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RFDelay: Byte; // 13
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DUC0RateHi: Byte; // 14
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DUC0RateLo: Byte; // 15
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DUC0Bits: Byte; // 16: default 24
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CWRampPeriod: Byte; // 17: ms, 0=default
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Reserved18: array[18..49] of Byte;
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MicLineSelect: Byte; // 50
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LineInGain: Byte; // 51: 0=-34.5dB .. 31=+12dB (шаг 1.5 dB)
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Reserved52: array[52..56] of Byte;
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StepAtten2: Byte; // 57: ADC2 atten during TX (0-31dB)
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StepAtten1: Byte; // 58: ADC1 atten during TX
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StepAtten0: Byte; // 59: ADC0 atten during TX
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end;
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// -------------------------------------------------------------------------
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// High Priority Packet (PC -> HW, port 1027)
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// Full packet is 1444 bytes but we define the key fields
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// -------------------------------------------------------------------------
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THighPriorityPacket = packed record
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Seq: array[0..3] of Byte;
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RunPTT: Byte; // 4: HP_RUN | HP_PTTn
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CWX0: Byte; // 5: [0]=CWX [1]=Dot [2]=Dash
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CWX1: Byte; // 6: reserved
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CWX2: Byte; // 7: reserved
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CWX3: Byte; // 8: reserved
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// Bytes 9-12: DDC0 frequency/phase word (Big-Endian)
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// Bytes 13-16: DDC1 ...
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// Bytes 17-328: DDC2..DDC79
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// Bytes 329-332: DUC0
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// Byte 345: DUC0 drive level (0-255)
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// Bytes 1398-1399: CAT over TCP port
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// Byte 1400: Transverter/audio enable
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// Byte 1401: Open Collector outputs
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// Bytes 1432-1435: Alex0 filter config
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// Byte 1443: Step Attenuator 0
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Data: array[9..1443] of Byte;
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end;
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// -------------------------------------------------------------------------
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// High Priority Status Packet (HW -> PC, port 1025)
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// -------------------------------------------------------------------------
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THighPriorityStatus = packed record
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Seq: array[0..3] of Byte;
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StatusBits: Byte; // 4: HPS_PTT/DOT/DASH/PLL_LOCKED
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ADCOverload: Byte; // 5: [0..7] = ADC0..7 overload
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ExciterPwr0Hi: Byte; // 6
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ExciterPwr0Lo: Byte; // 7
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ExciterPwr1: array[0..1] of Byte; // 8-9 (reserved)
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ExciterPwr2: array[0..1] of Byte; // 10-11 (reserved)
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ExciterPwr3: array[0..1] of Byte; // 12-13 (reserved)
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FwdPwrAlex0Hi: Byte; // 14
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FwdPwrAlex0Lo: Byte; // 15
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FwdPwrAlex1: array[0..1] of Byte; // 16-17 (reserved)
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FwdPwrAlex2: array[0..1] of Byte; // 18-19 (reserved)
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FwdPwrAlex3: array[0..1] of Byte; // 20-21 (reserved)
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RevPwrAlex0Hi: Byte; // 22
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RevPwrAlex0Lo: Byte; // 23
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RevPwrAlex1: array[0..1] of Byte; // 24-25 (reserved)
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RevPwrAlex2: array[0..1] of Byte; // 26-27 (reserved)
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RevPwrAlex3: array[0..1] of Byte; // 28-29 (reserved)
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FIFOOverflow: Byte; // 30: [3:0] overflow bits
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DDCFIFODepthHi: Byte; // 31
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DDCFIFODepthLo: Byte; // 32
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MicFIFODepthHi: Byte; // 33
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MicFIFODepthLo: Byte; // 34
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DUCFIFODepthHi: Byte; // 35
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DUCFIFODepthLo: Byte; // 36
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SpkFIFODepthHi: Byte; // 37
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SpkFIFODepthLo: Byte; // 38
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Unused39: array[39..48] of Byte;
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SupplyVoltsHi: Byte; // 49
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SupplyVoltsLo: Byte; // 50
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UserADC3Hi: Byte; // 51
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UserADC3Lo: Byte; // 52
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UserADC2Hi: Byte; // 53
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UserADC2Lo: Byte; // 54
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UserADC1Hi: Byte; // 55
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UserADC1Lo: Byte; // 56
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UserADC0Hi: Byte; // 57
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UserADC0Lo: Byte; // 58
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UserInputBits: Byte; // 59: IO4/IO5/IO6/IO8/IO2 etc.
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end;
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// -------------------------------------------------------------------------
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// Microphone Data Packet (HW -> PC, default port 1026)
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// -------------------------------------------------------------------------
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TMicDataPacket = packed record
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Seq: array[0..3] of Byte;
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Samples: array[0..63] of SmallInt; // 64 x 16-bit signed, big-endian
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end;
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// -------------------------------------------------------------------------
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// DDC I&Q Packet (HW -> PC, DDC0 default port 1035)
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// -------------------------------------------------------------------------
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TDDCIQPacket = packed record
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Seq: array[0..3] of Byte; // 0-3
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TimeStamp: array[0..7] of Byte; // 4-11: 64-bit VITA-49 timestamp
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BitsPerSample: array[0..1] of Byte; // 12-13
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SamplesPerFrame: array[0..1] of Byte;// 14-15
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// From byte 16: interleaved I/Q samples
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// For 24-bit: 3 bytes I, 3 bytes Q repeated
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// Max 238 IQ pairs for 24-bit = 1428 bytes, total packet = 1444
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IQData: array[0..1427] of Byte; // 16-1443
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end;
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// -------------------------------------------------------------------------
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// DDC Audio Packet (PC -> HW, default port 1028)
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// 64 Left + 64 Right 16-bit samples at 48ksps
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// -------------------------------------------------------------------------
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TDDCAudioPacket = packed record
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Seq: array[0..3] of Byte;
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// Interleaved Left/Right 16-bit samples (big-endian)
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// [L0_hi, L0_lo, R0_hi, R0_lo, L1_hi, L1_lo, R1_hi, R1_lo, ...]
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AudioData: array[0..255] of Byte; // 64 * 4 bytes
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end;
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// -------------------------------------------------------------------------
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// DUC I&Q Data Packet (PC -> HW, default port 1029)
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// 240 IQ pairs at 192ksps, 24-bit
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// -------------------------------------------------------------------------
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TDUCIQPacket = packed record
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Seq: array[0..3] of Byte;
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// 240 * 6 bytes = 1440 bytes
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IQData: array[0..1439] of Byte;
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end;
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// ---------------------------------------------------------------------------
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// Helper functions for Big-Endian packing/unpacking
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// ---------------------------------------------------------------------------
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// Pack a 32-bit word into 4 bytes (Big-Endian)
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procedure PackU32BE(Value: LongWord; out B: array of Byte; Offset: Integer = 0);
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// Unpack 4 bytes to a 32-bit word (Big-Endian)
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function UnpackU32BE(const B: array of Byte; Offset: Integer = 0): LongWord;
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// Pack a 16-bit word into 2 bytes (Big-Endian)
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procedure PackU16BE(Value: Word; out B: array of Byte; Offset: Integer = 0);
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// Unpack 2 bytes to a 16-bit word (Big-Endian)
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function UnpackU16BE(const B: array of Byte; Offset: Integer = 0): Word;
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// Convert frequency in Hz to phase word for HPSDR hardware
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function FreqToPhaseWord(FreqHz: Double): LongWord;
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// Convert phase word back to frequency
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function PhaseWordToFreq(PhaseWord: LongWord): Double;
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// Convert raw ADC value to supply voltage.
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// Returns -1.0 if the board has no supply voltage measurement.
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function ADCToSupplyVolts(RawADC: Word; BoardType: Integer): Double;
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// True when the board type reports supply voltage in HP Status.
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function BoardSupportsSupplyVoltage(BoardType: Integer): Boolean;
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// True when the board type reports supply current in HP Status.
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function BoardSupportsSupplyCurrent(BoardType: Integer): Boolean;
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// Convert raw ADC value to supply current in Amps (Board 5 / Orion MkII only)
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// Uses UserADC1 (bytes 55-56). Returns -1 for unsupported boards.
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// VoffMV/SensMVA — калибровка датчика (Thetis AmpVoff/AmpSens, ACS712-style).
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function ADCToSupplyCurrent(RawADC: Word; BoardType: Integer;
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VoffMV: Double = 360.0; SensMVA: Double = 120.0): Double;
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// Convert raw ADC value to RF power in Watts (ANAN-100)
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function ADCToWatts100(RawADC: Word): Double;
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// Convert raw ADC value to RF power in Watts (ANAN-10)
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function ADCToWatts10(RawADC: Word): Double;
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// Alex bridge FWD/REV detector → Watts, константы Thetis computeAlexFwdPower/
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// computeRefPower по модели трансивера:
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// 0 = ANAN-10/100/100B/100D (Vref 3.3V)
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// 1 = ANAN-200D / Orion (Vref 5.0V)
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// 2 = ANAN-7000DLE / Anvelina Pro 3 / G2 / Red Pitaya
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// 3 = ANAN-8000DLE / Orion MkII
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// IsRev — REV-детектор (свой bridge_volt/offset), Is6m — 6m-коррекция REV.
|
||
function AlexDetToWatts(RawADC: Word; DetModel: Integer;
|
||
IsRev, Is6m: Boolean): Double;
|
||
|
||
implementation
|
||
|
||
procedure PackU32BE(Value: LongWord; out B: array of Byte; Offset: Integer);
|
||
begin
|
||
B[Offset + 0] := (Value shr 24) and $FF;
|
||
B[Offset + 1] := (Value shr 16) and $FF;
|
||
B[Offset + 2] := (Value shr 8) and $FF;
|
||
B[Offset + 3] := Value and $FF;
|
||
end;
|
||
|
||
function UnpackU32BE(const B: array of Byte; Offset: Integer): LongWord;
|
||
begin
|
||
Result := (LongWord(B[Offset]) shl 24)
|
||
or (LongWord(B[Offset+1]) shl 16)
|
||
or (LongWord(B[Offset+2]) shl 8)
|
||
or LongWord(B[Offset+3]);
|
||
end;
|
||
|
||
procedure PackU16BE(Value: Word; out B: array of Byte; Offset: Integer);
|
||
begin
|
||
B[Offset + 0] := (Value shr 8) and $FF;
|
||
B[Offset + 1] := Value and $FF;
|
||
end;
|
||
|
||
function UnpackU16BE(const B: array of Byte; Offset: Integer): Word;
|
||
begin
|
||
Result := (Word(B[Offset]) shl 8) or Word(B[Offset+1]);
|
||
end;
|
||
|
||
function FreqToPhaseWord(FreqHz: Double): LongWord;
|
||
begin
|
||
// phase_word = 2^32 * freq / DSP_CLOCK
|
||
Result := Round(4294967296.0 * FreqHz / DSP_CLOCK_HZ);
|
||
end;
|
||
|
||
function PhaseWordToFreq(PhaseWord: LongWord): Double;
|
||
begin
|
||
Result := PhaseWord * DSP_CLOCK_HZ / 4294967296.0;
|
||
end;
|
||
|
||
function ADCToSupplyVolts(RawADC: Word; BoardType: Integer): Double;
|
||
begin
|
||
// Protocol Appendix A gives the ADC reference voltage only.
|
||
// The PCB voltage divider (from Thetis source) must also be applied.
|
||
// Board 0 (Atlas): no supply voltage measurement.
|
||
// Boards 1,2,3 (Hermes/Angelia): Vref=3.3V, PCB divider R1=4.7kΩ/R2=0.82kΩ.
|
||
// Board 4 (Orion): protocol reports supply voltage with a 5.0V constant.
|
||
// Board 5 (Orion MkII): Vref=5.0V, PCB divider R1=22kΩ/R2=1.1kΩ.
|
||
// NOTE: for board 5 caller must pass UserADC0, not supply_volts bytes.
|
||
// Other boards: not available (return -1).
|
||
case BoardType of
|
||
1, 2, 3: Result := (RawADC / 4095.0) * 3.3 * ((4.7 + 0.82) / 0.82);
|
||
4: Result := (RawADC / 4095.0) * 5.0;
|
||
5: Result := (RawADC / 4095.0) * 5.0 * ((22.0 + 1.0) / 1.1);
|
||
else Result := -1.0;
|
||
end;
|
||
end;
|
||
|
||
function BoardSupportsSupplyVoltage(BoardType: Integer): Boolean;
|
||
begin
|
||
Result := BoardType in [1, 2, 3, 4, 5];
|
||
end;
|
||
|
||
function BoardSupportsSupplyCurrent(BoardType: Integer): Boolean;
|
||
begin
|
||
Result := BoardType = 5;
|
||
end;
|
||
|
||
function ADCToSupplyCurrent(RawADC: Word; BoardType: Integer;
|
||
VoffMV: Double; SensMVA: Double): Double;
|
||
begin
|
||
// Board 5 (Orion MkII): UserADC1, Vref=5V → mV = adc/4095*5000.
|
||
// Formula: amps = (mV - Voff) / Sens. Дефолты Voff=360мВ, Sens=120мВ/А
|
||
// (Thetis, ACS712-style); переопределяются калибровкой.
|
||
if (BoardType = 5) and (SensMVA > 0) then
|
||
begin
|
||
Result := ((RawADC / 4095.0) * 5000.0 - VoffMV) / SensMVA;
|
||
if Result < 0.0 then Result := 0.0;
|
||
end else
|
||
Result := -1.0;
|
||
end;
|
||
|
||
function ADCToWatts100(RawADC: Word): Double;
|
||
var
|
||
V: Double;
|
||
begin
|
||
// W = (ADC/4095 * 3.3)^2 / 0.095 (ANAN-100, 0-150W range)
|
||
V := (RawADC / 4095.0) * 3.3;
|
||
Result := (V * V) / 0.095;
|
||
end;
|
||
|
||
function ADCToWatts10(RawADC: Word): Double;
|
||
var
|
||
V: Double;
|
||
begin
|
||
// W = (ADC/4095 * 3.3)^2 / 0.09 (ANAN-10, 0-20W range)
|
||
V := (RawADC / 4095.0) * 3.3;
|
||
Result := (V * V) / 0.09;
|
||
end;
|
||
|
||
function AlexDetToWatts(RawADC: Word; DetModel: Integer;
|
||
IsRev, Is6m: Boolean): Double;
|
||
var
|
||
Bridge, Vref, V: Double;
|
||
CalOff: Integer;
|
||
begin
|
||
// Константы из Thetis (console.cs computeAlexFwdPower / computeRefPower).
|
||
// W = ((ADC - CalOff)/4095 * Vref)^2 / Bridge.
|
||
case DetModel of
|
||
1: begin // ANAN-200D / Orion
|
||
Vref := 5.0;
|
||
if IsRev then begin
|
||
Bridge := 0.108; if Is6m then Bridge := 0.5;
|
||
CalOff := 2;
|
||
end else begin
|
||
Bridge := 0.108; CalOff := 4;
|
||
end;
|
||
end;
|
||
2: begin // ANAN-7000DLE / Anvelina Pro 3 / G2 / Red Pitaya
|
||
Vref := 5.0;
|
||
if IsRev then begin
|
||
Bridge := 0.15; if Is6m then Bridge := 0.7;
|
||
CalOff := 28;
|
||
end else begin
|
||
Bridge := 0.12; CalOff := 32;
|
||
end;
|
||
end;
|
||
3: begin // ANAN-8000DLE / Orion MkII
|
||
Vref := 5.0; Bridge := 0.08;
|
||
if IsRev then CalOff := 16 else CalOff := 18;
|
||
end;
|
||
else begin // 0: ANAN-10/100/100B/100D
|
||
Vref := 3.3;
|
||
if IsRev then begin
|
||
Bridge := 0.095; if Is6m then Bridge := 0.5;
|
||
CalOff := 3;
|
||
end else begin
|
||
Bridge := 0.095; CalOff := 6;
|
||
end;
|
||
end;
|
||
end;
|
||
V := ((RawADC - CalOff) / 4095.0) * Vref;
|
||
if V < 0 then V := 0;
|
||
Result := (V * V) / Bridge;
|
||
end;
|
||
|
||
end.
|