ew8bakandClaude Opus 4.8 b2fa2756cf docs(slices): draft Stage 3 notes (HW DDC design + UI concept) ...

Record grounded data-path analysis, per-DDC/RX2 deltas, the soft-vs-hard
WDSP channel split, preliminary decisions (4-6 hard DDCs, static first),
and the UI concept (edge markers, slices rail, ADC badge). Marked as a
work-in-progress draft.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

2026-07-02 14:36:31 +03:00

..

ANDROMEDA.md

fix(cat): align Andromeda panel mapping with real G2 hardware (Thetis)

2026-06-29 16:11:12 +03:00

CAT_STATUS.md

feat(cat): wire split/FM/CTUN/AGC-T CAT commands to controller

2026-06-26 10:35:35 +03:00

openHPSDR Ethernet Protocol v4.3.docx

start work tx

2026-03-26 22:50:55 +03:00

PLUTO_INTEGRATION_PLAN.md

feat: web RF-AGC + QO-100 RX MUTE controls (Pluto)

2026-06-24 11:02:34 +03:00

SLICES_PLAN.md

docs(slices): draft Stage 3 notes (HW DDC design + UI concept)

2026-07-02 14:36:31 +03:00

WDSP Guide, Rev 1.29.pdf

start work tx

2026-03-26 22:50:55 +03:00